Abstract | ||
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The pressure to create a working System on Chip design as early as possible leads designers to consider using a platform based design method. In this approach, designing an application is a matter of selecting from a set of standard components with compatible specifications. Subsequently, a formal verification platform can be constructed. The formal verification platform provides an environment to analysed the combined properties of the design. In this paper, we present a methodology to do formal System on Chip analysis by developing generic formal components that can be integrated in a formal verification platform. First, we develop reusable formal properties of standard components. Second, we define a generic formal platform in which components of System on Chip design can be integrated. The platform contains basic components such as a standard bus protocol and a processor. Third, we combine the properties of standard components and obtain a set of refined properties of the system. We use these properties to develop the required specifications of the remaining components. |
Year | DOI | Venue |
---|---|---|
2003 | 10.1007/978-3-540-39893-6_5 | Lecture Notes in Computer Science |
Keywords | Field | DocType |
formal verification,system on chip | Formal system,System on a chip,Computer science,Runtime verification,Formal specification,Platform-based design,Integrated design,Formal methods,Formal verification,Embedded system | Conference |
Volume | ISSN | Citations |
2885 | 0302-9743 | 5 |
PageRank | References | Authors |
0.51 | 12 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Kong Woei Susanto | 1 | 81 | 5.22 |
Thomas F. Melham | 2 | 384 | 35.63 |