Name
Abstract | ||
|---|---|---|
The current level of circuit integration led to complex designs encompassing full systems on a single chip, known as System-on-a-Chip (SoC). In order to predict the best design options and reduce the design costs, designers are required to perform a large design space exploration on early stages of the design. To speed up this process, Electronic Design Automation (EDA) tools are employed to model and experiment with the system. ArchC is an "Architecture Description Language" (ADL) and a set of tools that can be leveraged to automatically build SoC simulators based on high-level system models, enabling easy and fast design space exploration in early stages of the design. Currently, ArchC is capable of automatically generating hardware simulators, assemblers, and linkers for a given architecture model. In this work, we present ACCGen, an automatic Compiler Generator for ArchC, the missing link on the automatic generation of compiler tool chains for ArchC. Our experimental results show that compilers generated by ACCGen are correct for Mibench applications. They compare, as well, the generated code quality with LLVM and gcc, two well-known open-source compilers. We also show that ACCGen is fast and has little impact on the design space exploration turnaround time, allowing the designer to, using an easy and fully automated workflow, completely assess the outcome of architectural changes in less than 2 minutes. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/SBAC-PAD.2012.33 | Computer Architecture and High Performance Computing |
Keywords | Field | DocType |
large design space exploration,architecture model,automatic archc compiler generator,fast design space exploration,early stage,automatic generation,best design option,design space exploration turnaround,automatic compiler generator,design cost,complex design,electronic design automation,system on chip,integrated circuit design,public domain software | Computer architecture,System on a chip,Computer science,Parallel computing,Compiler,Integrated circuit design,Electronic design automation,Software quality,Workflow,Design space exploration,Architecture description language | Conference |
ISSN | ISBN | Citations |
1550-6533 | 978-1-4673-4790-7 | 3 |
PageRank | References | Authors |
0.39 | 9 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rafael Auler | 1 | 20 | 3.19 |
| Paulo Cesar Centoducatte | 2 | 6 | 0.81 |
| Edson Borin | 3 | 131 | 10.48 |