Name
Abstract | ||
|---|---|---|
In future microprocessors, communication will emerge as the major bottleneck. The authors advocate composing future interconnects of some wires that minimize latency, some that maximize bandwidth, and some that minimize power. A microarchitecture aware of these wire characteristics can steer on-chip data transfers to the most appropriate wires, thus improving performance and saving energy. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/MM.2006.123 | IEEE Micro |
Keywords | Field | DocType |
leveraging wire properties,on-chip data transfer,future interconnects,microarchitecture level,major bottleneck,appropriate wire,wire characteristic,future microprocessors,chip,data transfer | Bottleneck,Computer architecture,Latency (engineering),Computer science,Parallel computing,Bandwidth (signal processing),Microarchitecture,Embedded system | Journal |
Volume | Issue | ISSN |
26 | 6 | 0272-1732 |
Citations | PageRank | References |
2 | 0.40 | 6 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rajeev Balasubramonian | 1 | 2302 | 116.79 |
| Naveen Muralimanohar | 2 | 1295 | 57.58 |
| Karthik Ramani | 3 | 1328 | 81.38 |
| Liqun Cheng | 4 | 49 | 2.96 |
| John B. Carter | 5 | 1785 | 162.82 |