Name
Title | ||
|---|---|---|
A comprehensive study of stress induced leakage current using a floating gate structure for direct applications in EEPROM memories |
Abstract | ||
|---|---|---|
The aim of this study is to obtain from experimental data a reliable approach for predicting the impact of temperature on data retention in EEPROM memories. Using a floating gate dedicated structure, we present stress induced leakage current results and characterization in terms of AC generation, annealing kinetics and temperature activation in 6.8nm SiO2 tunneling oxide used in standard EEPROM products. We propose a simple way to deal with these three aspects in order to describe SILC evolution during retention phases corresponding to an oxide floating gate potential lower than 2V. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1016/j.microrel.2007.07.040 | Microelectronics Reliability |
Keywords | Field | DocType |
stress induced leakage current,kinetics | Tunnel effect,EEPROM,Quantum tunnelling,Oxide,Data retention,Leakage (electronics),Electronic engineering,Engineering,Integrated circuit,SILC | Journal |
Volume | Issue | ISSN |
47 | 9 | 0026-2714 |
Citations | PageRank | References |
1 | 0.47 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| D. Pic | 1 | 3 | 1.76 |
| D. Goguenheim | 2 | 10 | 6.40 |
| J.L. Ogier | 3 | 3 | 1.80 |