Name
Abstract | ||
|---|---|---|
We present a novel loop scheduling approach which optimally exploits instruction-level parallelism. We develop a new flow graph model for the resource constraints allowing a more efficient implementation. The method supports heterogeneous processor architectures and pipelined functional units. Our Linear Programming implementation produces an optimum loop schedule, making the technique applicable to production compilation and hardware parametrization. Compared to earlier approaches, the approach can provide faster loop schedules and a significant reduction of the problem complexity and solution time. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/INTERA.2004.1299506 | EIGHTH WORKSHOP ON INTERACTION BETWEEN COMPILERS AND COMPUTER ARCHITECTURES, PROCEEDINGS |
Keywords | Field | DocType |
processor architecture,linear program,computational complexity,linear programming,instruction sets,data flow analysis,functional unit | Instruction-level parallelism,Control flow graph,Instruction set,Computer science,Loop fission,Parallel computing,Loop tiling,Loop inversion,Schedule,Loop scheduling | Conference |
Citations | PageRank | References |
2 | 0.38 | 11 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jan Müller | 1 | 14 | 4.33 |
| Dirk Fimmel | 2 | 48 | 6.45 |
| Renate Merker | 3 | 159 | 20.59 |