Name
Abstract | ||
|---|---|---|
The purpose of this paper is to present a design methodology that complements existing methodologies by addressing the upper and the lower extremes of the design flow. The aim of the methodology is to increase design and product quality. At system level, emphasis is given to architecture generation, reconfiguration and quality assessment. Quality metrics and criteria, focused on design and test issues, are used for the purpose. At physical level, a Defect-Oriented Test (DOT) approach and test reuse is the basis of the methodology to estimate test effectiveness, or Defects Coverage. Tools, that implemented the methodology, are presented. Results are shown for a public domain PIC processor, used as a SOC embedded core. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/ISQED.2000.838874 | ISQED |
Keywords | Field | DocType |
design flow,architectural level,system level,quality assessment,electronic design,test issue,test effectiveness,product quality,quality metrics,test coverage,design methodology,test reuse,physical level,quality control,system on a chip,integrated circuit design,ducts,public domain,software quality,hardware,system testing | Design for testing,Code coverage,Test Management Approach,Systems engineering,Computer science,Electronic engineering,Design methods,Design flow,Iterative design,Physical design,Reliability engineering,Control reconfiguration | Conference |
ISBN | Citations | PageRank |
0-7695-0525-2 | 1 | 0.36 |
References | Authors | |
11 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| O. P. Dias | 1 | 12 | 2.51 |
| Jorge Semião | 2 | 57 | 12.11 |
| M. B. Santos | 3 | 1 | 0.36 |
| I. M. Teixeira | 4 | 12 | 2.17 |
| J. P. Teixeira | 5 | 44 | 6.26 |