Jorge Semião - Citegraph

Author Info

Name	Affiliation	Papers
JORGE SEMIÃO	Univ Tecn Lisboa, IST, Dept Elect & Comp Engn, P-1100 Lisbon, Portugal	30
Collaborators	Citations	PageRank
70	57	12.11
Referers	Referees	References
140	408	226

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100408

Publications (30 rows)

Collaborators (70 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Fault-Tolerance In Field Programmable Gate Array With Dynamic Voltage And Frequency Scaling	0	0.34	2015
Fault-tolerance in FPGA focusing power reduction or performance enhancement	0	0.34	2015
Performance sensor for tolerance and predictive detection of delay-faults	1	0.36	2014
A distributed load scheduling mechanism for micro grids	0	0.34	2014
Aging Monitoring With Local Sensors In Fpga-Based Designs	1	0.35	2013
Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion	2	0.38	2013
Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits	0	0.34	2012
The influence of clock-gating on NBTI-induced delay degradation	1	0.35	2012
Aging-Aware Power or Frequency Tuning With Predictive Fault Detection.	5	0.44	2012
Performance Failure Prediction Using Built-In Delay Sensors in FPGAs	3	0.41	2011
On-Line Bist For Performance Failure Prediction Under Nbti-Induced Aging In Safety-Critical Applications	0	0.34	2011
Lower VDD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing.	0	0.34	2011
Adaptive Error-Prediction Flip-Flop For Performance Failure Prediction With Aging Sensors	11	0.77	2011
Investigating the Use of BICS to detect resistive-open defects in SRAMs	0	0.34	2010
Impact Of Power Supply Voltage Variations On Fpga-Based Digital Systems Performance	9	0.79	2010
Predictive error detection by on-line aging monitoring	5	0.57	2010
Delay-Fault Tolerance To Power Supply Voltage Disturbances Analysis In Nanometer Technologies	2	0.39	2009
Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits	2	0.39	2008
Time Management For Low-Power Design Of Digital Systems	3	0.44	2008
Robust solution for synchronous communication among multi clock domains.	1	0.39	2008
Delay Modeling For Power Noise And Temperature-Aware Design And Test Of Digital Systems	1	0.35	2008
Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits	2	0.39	2008
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations	4	0.51	2007
Enhancing the Tolerance to Power-Supply Instability in Digital Circuits	0	0.34	2007
On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits	0	0.34	2007
Functional-oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage	1	0.37	2006
Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes	2	0.37	2006
Embedded tutorial: TRP: integrating embedded test and ATE	0	0.34	2001
Quality of Electronic Design: From Architectural Level to Test Coverage	1	0.36	2000
From system level to defect-oriented test: a case study	0	0.34	1999