Paper Info
Title
Design of ternary D flip-flop using one latch with neuron-MOS literal circuit
Abstract
A new ternary D flip-flop using one latch is presented. In order to meet the non-transparent demand in flip-flops, the narrow pulses produced by the race-hazard of the clock signal are used to control the latch. In the proposed design scheme, literal functions are realized by using neuron-MOS transistors. Then, the pass transistors used to pass ternary signal are controlled by the outputs of the literal circuit to realize ternary inverter and identity cell. As the variable threshold voltage can be achieved easily in neuron-MOS literal circuit, the proposed ternary circuit has simple structure. Compared to the traditional voltage-mode MVL flip-flops, the proposed ternary flip-flop can be fabricated by standard CMOS process with a double-ploy layer, without multi-level ion implantation applied in the conventional voltage-mode multiple-valued circuits. HSPICE simulation results using TSMC 0.35μm double-poly 4-metal CMOS process parameters have verified the characteristics of the proposed scheme. The proposed construction can be easily extended to the design of multiple-valued edge-triggered flip-flop with a higher radix.
Year
DOI
Venue
2013
10.1109/ICNC.2013.6817984
ICNC
Keywords
Field
DocType
nontransparent demand,ion implantation,voltage-mode multiple-valued circuits,neuron-mos literal circuit,neuron-mos transistor,double-ploy layer,ternary d flip-flop design,pass transistors,floatinggate mos,race-hazard,proposed voltage-mode ternary flip-flop,flip-flop,standard cmos process,edge-triggered flip-flop,ternary flip-flop,clock signal,variable threshold voltage,size 0.35 mum,ternary d flip-flop,proposed construction,tsmc 4-metal process parameters,multiple-valued edge-triggered flip-flop,cmos circuits,multilevel ion implantation,proposed circuit,ternary circuit,integrated circuit design,cmos digital integrated circuits,latch,voltage-mode mvl flip-flops,pass ternary signal,identity cell,flip-flops,ternary literal function,ternary inverter,2-ploy 4-metal cmos technology,multiple-valued logic,hspice simulation,logic gates,cmos integrated circuits,transistors,race hazard
Clock signal,Inverter,Mathematical optimization,Computer science,Ternary operation,Electronic engineering,Ternary signal,Electronic circuit,Flip-flop,Transistor,Threshold voltage,Embedded system
Conference
Citations 
PageRank 
References 
0
0.34
7
Authors
4
Name
Order
Citations
PageRank
Xuanchang Zhou112.75
Guoqiang Hang275.83
Danyan Zhang322.46
Xiaohui Hu472.27