Name
Abstract | ||
|---|---|---|
In this paper, we present two alternative architectures and FPGA implementations of the 64-bit NESSIE proposal, MISTY1 block cipher. The first architecture is suitable for applications with high-performance requirements. A throughput of up to 12.6 Gbps can be achieved at a clock frequency of 168 MHz. The main characteristic of this architecture is that uses RAM blocks embedded in modern FPGA devices in order to implement the S-boxes defined in the block cipher algorithm. The second architecture can be used in implementing applications on area-constrained systems. It utilizes feedback logic and inner pipeline with negative edge-triggered register. This technique shortens the critical path, without increasing the latency of the MISTY1 algorithm execution. Compared with an implementation without inner pipeline, performance improvement of 97% is achieved. The measured throughput of the second architecture implementation is 561 Mbps at 79 MHz. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1142/S0218126606003362 | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS |
Keywords | Field | DocType |
MISTY1,block cipher,cryptography,NESSIE,inner pipeline,negative edge-triggered register,FPGA | MISTY1,Block cipher,CBC-MAC,Computer science,NESSIE,Field-programmable gate array,Critical path method,Triple DES,Clock rate,Embedded system | Journal |
Volume | Issue | ISSN |
15 | 6 | 0218-1266 |
Citations | PageRank | References |
6 | 0.60 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Paris Kitsos | 1 | 98 | 21.99 |
| Michalis D. Galanis | 2 | 94 | 15.60 |
| Odysseas G. Koufopavlou | 3 | 151 | 30.92 |