Michalis D. Galanis

Author Info

Name	Affiliation	Papers
MICHALIS D. GALANIS	VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras, Greece	36
Collaborators	Citations	PageRank
23	94	15.60
Referers	Referees	References
229	377	425

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100377

Publications (36 rows)

Collaborators (23 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays	1	0.35	2009
Resource aware mapping on coarse grained reconfigurable arrays	16	0.70	2009
Novel Hardware Implementation of the Cipher Message Authentication Code	0	0.34	2008
Performance and energy consumption improvements in microprocessor systems utilizing a coprocessor data-path	2	0.40	2008
Speedups from extending embedded processors with a high-performance coarse-grained reconfigurable data-path	0	0.34	2008
Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path	0	0.34	2007
Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path	0	0.34	2007
Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture	5	0.45	2007
A unified evaluation framework for coarse grained reconfigurable array architectures	5	0.44	2007
Compiler assisted architectural exploration for coarse grained reconfigurable arrays	1	0.36	2007
Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path	0	0.34	2007
Speedups in embedded systems with a high-performance coprocessor datapath	1	0.37	2007
Performance optimization of embedded applications in a hybrid reconfigurable platform	0	0.34	2007
Mapping Dsp Applications On Processor/Coarse-Grain Reconfigurable Array Architectures	2	0.38	2006
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic	0	0.34	2006
Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware	2	0.38	2006
Architectures and FPGA Implementations of the 64-Bit MISTY1 Block Cipher	6	0.60	2006
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units	6	0.47	2006
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems	1	0.53	2006
Resource Constrained Modulo Scheduling For Coarse-Grained Reconfigurable Arrays	0	0.34	2006
Performance improvements from partitioning applications to FPGA hardware in embedded SoCs	2	0.40	2006
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures	10	0.72	2006
Partitioning DSP applications to different granularity reconfigurable hardware.	0	0.34	2005
An Fpga Implementation of the Gprs Encryption Algorithm 3 (gea3)	0	0.34	2005
A method for partitioning applications in hybrid reconfigurable architectures	2	0.40	2005
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays	11	0.76	2005
Comparison of the Hardware Implementation of Stream Ciphers	4	0.83	2005
Performance gains from partitioning embedded applications in Processor-FPGA socs	0	0.34	2005
A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels	6	0.47	2005
Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs	2	0.39	2005
High-Speed Hardware Implementations Of The Kasumi Block Cipher	5	0.62	2004
A high performance data-path to accelerate DSP kernels.	0	0.34	2004
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path	3	0.46	2004
An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications	0	0.34	2004
Architectures and Hardware Implementations of the 64-bit MISTY1 Block Cipher.	0	0.34	2004
Power aware data type refinement on the HIPERLAN/2.	1	0.37	2003