Name
Abstract | ||
|---|---|---|
This paper proposes a simulation-based methodology for validation of a system under design in an early phase of development. The key element of this approach is the visual specification, as Live Sequence Charts (LSCs), of the properties to be checked. The LSCs are automatically translated into the input format for the SystemC-based checker engine, which indicates during simulation, if the property is fulfilled or produces a counter-example, if the property is violated. The entire process from the visual property specification to the checking is largely automated, which makes our approach accessible even for users which have not been trained in formal methods. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1145/581199.581240 | ISSS |
Keywords | Field | DocType |
visual property specification,formal method,early phase,visual specification,key element,live sequence charts,visual approach,system level design,systemc-based checker engine,simulation-based methodology,entire process,input format,high level synthesis,formal specification,simulation,system on chip | Programming language,System on a chip,Computer science,High-level synthesis,Formal specification,Real-time computing,SystemC,Live sequence charts,Visual approach,Formal methods,System level | Conference |
ISBN | Citations | PageRank |
1-58113-576-9 | 2 | 0.43 |
References | Authors | |
9 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jochen Klose | 1 | 151 | 10.10 |
| Thomas Kropf | 2 | 326 | 59.09 |
| Jürgen Ruf | 3 | 122 | 23.04 |