Name
Affiliation
Papers
JÜRGEN RUF
University of Tübingen
47
Collaborators
Citations 
PageRank 
53
122
23.04
Referers 
Referees 
References 
217
450
313
Search Limit
100450
Title
Citations
PageRank
Year
Using Robustness Testing to Handle Incomplete Verification Results When Combining Verification and Testing Techniques.00.342017
Efficient Testing of Different Loop Paths10.362015
Efficient Fault Localization During Replay of Embedded Software00.342015
Scalable and Optimized Hybrid Verification of Embedded Software20.382015
Erkennen von Speicherverletzungen im Testbetrieb von eingebetteter Software.00.342014
Increasing Software Reliability by Integrating Formal Verification and Robustness Testing.00.342014
LoCEG: Local Preprocessing in SAT-Solving through Counter-Example Generation.00.342014
More Flexible Object Invariants with Less Specification Overhead.10.382014
A Software Testing Framework to Integrate Formal Verification Results.00.342013
Beschleunigte Robustheitstests für verhaltensbeschreibende Zustandsmaschinen.00.342013
Optimized Static Parameter Assignment for Semiformal Software Verification.10.362012
DWARF-driven Equivalence Checking of UML Statecharts and Software Components.00.342011
Scalable and Extendable Hybrid Verification Platform.10.362011
State-based Analysis and UML-driven Equivalence Checking for C++ State Machines10.372010
Towards assertion-based verification of heterogeneous system designs90.742010
Semiformal verification of temporal properties in automotive hardware dependent software70.502009
Verification of temporal properties in automotive embedded software80.602008
Advanced Assertion-Based Design For Mixed-Signal Verification20.482008
Transaction Modeling and RTL Simulation Analysis.10.382007
Semiformal Verification of Temporal Properties in Embedded Software.10.402007
Grid Based Fast Falsification For Bounded Property Checking00.342007
UML/SysML-Systemanalyse zur Generierung von formalen Verifikationseigenschaften für verschiedene Abstraktionsebenen.00.342007
Automatische Eigenschaftsextraktion auf Systemebene aus SystemC Modellen.00.342006
Distributed Symbolic Bounded Property Checking10.372006
Fast falsification based on symbolic bounded property checking00.342006
Monitoring-based Formal Hardware Verification.00.342006
Overlap reduction in symbolic system traversal10.352005
Efficient and Customizable Integration of Temporal Properties00.342005
Transactional Level Verification and Coverage Metrics by Means of Symbolic Simulation.61.592004
Dynamic guiding of bounded property checking30.372004
Symbolic Verification and Analysis of Discrete Timed Systems20.572003
Using Symbolic Simulation for Bounded Property Checking00.342003
Optimized Temporal Logic Compilation30.502003
A visual approach to validating system level designs20.432002
Combination of Simulation and Formal Verification.00.342002
Data Analysis of Timed Finite State Systems.00.342001
Customer-Oriented Systems Design through Virtual Prototypes10.392001
Formale Verifikation diskreter Echtzeitsysteme (Formal Verification of Discrete Real-Time Systems)00.342001
Correctness of Efficient Real-Time Model Checking20.412001
RAVEN: Real-Time Analyzing and Verification Environment161.222001
A Toolset for the Symbolic Examination of Finite State Transition Systems.10.392000
Analyzing real-time systems50.802000
Do You Trust Your Model Checker?30.432000
Structured English for Model Checking Specification121.082000
Using MTBDDs for Compostion and Model Checking of Real-Time Systems70.601998
Symbolic model checking for a discrete clocked temporal logic with intervals211.781997
A New Algorithm for Discrete Timed Symbolic Model Checking10.361997