Name
Abstract | ||
|---|---|---|
Turbo decoders inherently have a large latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, two types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes introduce no performance degradation in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presented |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/ICASSP.2001.940542 | ICASSP |
Keywords | Field | DocType |
computation units,pipeline-interleaving,turbo codes,simulation results,hybrid parallel decoding,area-efficient high speed decoding,decoding latency,parallel architectures,area-efficient parallel decoding,awgn channel,parallel turbo decoding architectures,turbo/map decoders,bpsk,turbo decoders,iterative decoding,throughput,storage requirement,pipeline processing,parallel processing,computational modeling,degradation,concurrent computing | Turbo,Sequential decoding,Computer science,Latency (engineering),Turbo code,Parallel computing,Serial concatenated convolutional codes,Throughput,Decoding methods,List decoding | Conference |
Volume | ISSN | ISBN |
4 | 1520-6149 | 0-7803-7041-4 |
Citations | PageRank | References |
5 | 0.92 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhongfeng Wang | 1 | 59 | 11.49 |
| Zhipei Chi | 2 | 66 | 6.87 |
| keshab k parhi | 3 | 3235 | 369.07 |