Name
Title | ||
|---|---|---|
Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. |
Abstract | ||
|---|---|---|
This paper presents a procedure of pre-characterization dedicated to the logic and timing simulation of IR-drop induced delays in a logic Block Under Test (BUT) embedded in a chip. The proposed pre-characterization is twofold: the pre-characterization of the library on the one hand and the pre-characterization of the power grid on the other hand. Both should be computed only once for a given technology. Based on this pre-characterization, an original algorithm can be built allowing to perform a per-cycle delay simulation of the logic BUT while taking into account the whole chip IR-drop impact on the simulated block. The simulation is based on a realistic resistive model of the Power Distribution Network (PDN). |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/LATW.2013.6562657 | Latin American Test Workshop |
Keywords | Field | DocType |
Digital CMOS IC,Test,Power Noise,IR-drop,Simulation | Logic gate,Power network design,Capacitance,Computer science,Resistive touchscreen,Distribution networks,Chip,Electronic engineering,Logic simulation,Logic block | Conference |
ISSN | Citations | PageRank |
2373-0862 | 2 | 0.43 |
References | Authors | |
5 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Aparicio | 1 | 9 | 0.88 |
| Mariane Comte | 2 | 61 | 7.44 |
| F. Azaïs | 3 | 188 | 24.15 |
| Michel Renovell | 4 | 749 | 96.46 |
| J. Jiang | 5 | 55 | 9.59 |
| Ilia Polian | 6 | 889 | 78.66 |
| Bernd Becker | 7 | 855 | 73.74 |