| Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies. | 0 | 0.34 | 2019 |
| A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells | 0 | 0.34 | 2019 |
| Modeling and Detectability of Full Open Gate Defects in FinFET Technology | 0 | 0.34 | 2019 |
| B-open: A New Defect in Nanometer Technologies due to SADP Process | 0 | 0.34 | 2019 |
| Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies | 0 | 0.34 | 2018 |
| Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. | 0 | 0.34 | 2018 |
| Spot defect modeling: Past and evolution | 0 | 0.34 | 2017 |
| Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology | 0 | 0.34 | 2017 |
| Analysis of short defects in FinFET based logic cells | 0 | 0.34 | 2017 |
| Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies. | 1 | 0.36 | 2017 |
| Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations | 2 | 0.38 | 2016 |
| Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI -- LVT and RVT Configurations | 2 | 0.41 | 2016 |
| A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy | 0 | 0.34 | 2015 |
| Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell | 2 | 0.42 | 2015 |
| Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies. | 5 | 0.55 | 2015 |
| Toward Adaptation of ADCs to Operating Conditions through On-chip Correction | 0 | 0.34 | 2015 |
| Power-aware voltage tuning for STT-MRAM reliability | 2 | 0.40 | 2015 |
| Testing For Gate Oxide Short Defects Using The Detectability Interval Paradigm | 0 | 0.34 | 2014 |
| Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements | 0 | 0.34 | 2014 |
| Sram cell stability metric under transient voltage noise. | 1 | 0.38 | 2014 |
| DTIS 2014 foreword. | 0 | 0.34 | 2014 |
| Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. | 2 | 0.43 | 2013 |
| Accurate and efficient analytical electrical model of antenna for NFC applications | 1 | 0.42 | 2013 |
| Making predictive analog/RF alternate test strategy independent of training set size | 13 | 0.76 | 2012 |
| Low voltage testing for interconnect opens under process variations | 1 | 0.36 | 2012 |
| A New Methodology For Realistic Open Defect Detection Probability Evaluation Under Process Variations | 1 | 0.36 | 2011 |
| Influence of parasitic memory effect on single-cell faults in SRAMs | 1 | 0.37 | 2011 |
| Digital Test Method for Embedded Converters with Unknown-Phase Harmonics | 0 | 0.34 | 2011 |
| Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric | 4 | 0.43 | 2011 |
| Parasitic memory effect in CMOS SRAMs. | 1 | 0.38 | 2010 |
| SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges | 8 | 0.53 | 2009 |
| Functional Testing of Processor Cores in FPGA-Based Applications | 3 | 0.56 | 2009 |
| A Simulator of Small-Delay Faults Caused by Resistive-Open Defects | 29 | 1.07 | 2008 |
| Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008 | 72 | 11.53 | 2008 |
| Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008 | 50 | 5.29 | 2008 |
| Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis | 6 | 0.50 | 2007 |
| Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation | 0 | 0.34 | 2007 |
| A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs | 9 | 0.82 | 2006 |
| Call for Papers and Participation | 0 | 0.34 | 2006 |
| An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs | 3 | 0.44 | 2006 |
| Functional Test of Field Programmable Analog Arrays | 4 | 0.56 | 2006 |
| Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays | 7 | 0.75 | 2005 |
| Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies | 5 | 0.45 | 2005 |
| Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs | 1 | 0.43 | 2005 |
| Built-in self-test of global interconnects of field programmable analog arrays | 5 | 0.50 | 2005 |
| Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks | 4 | 0.57 | 2005 |
| Modeling Feedback Bridging Faults With Non-Zero Resistance | 5 | 0.46 | 2005 |
| Scan Design and Secure Chip | 49 | 4.63 | 2004 |
| A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs | 18 | 1.14 | 2004 |
| An Approach to the Built-In Self-Test of Field Programmable Analog Arrays | 8 | 0.75 | 2004 |
