Name
Abstract | ||
|---|---|---|
Nanomagnet Logic (NML) is an emerging device architecture that performs logic operations through fringing field interactions between nano-scale magnets. The design space for NML circuits is large and so far there exists no systematic approach for determining the parameter values (e.g., device-to-device spacings, clocking field strength etc.) to generate a predictable design solution. This paper presents a formal methodology for designing NML circuits that marshals the design parameters to generate a layout that is guaranteed to evolve correctly in time at 0K. The approach is further augmented to identify functional design targets when considering thermal noise associated with higher temperatures. The approach is applied to identify layouts for a 2-input AND gate, a "corner turn," and a 3-input majority gate. Layouts are verified through simulations both at 0K and room temperature (300K). |
Year | DOI | Venue |
|---|---|---|
2013 | 10.7873/DATE.2013.360 | DATE |
Keywords | Field | DocType |
layout,igbt,switches,logic gates | Logic gate,Computer science,Functional design,Noise (electronics),Insulated-gate bipolar transistor,Electronic engineering,Nanomagnet,Boolean algebra,Electronic circuit,AND gate | Conference |
ISSN | Citations | PageRank |
1530-1591 | 1 | 0.44 |
References | Authors | |
1 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Indranil Palit | 1 | 57 | 6.28 |
| Xiaobo Sharon Hu | 2 | 2004 | 208.24 |
| Joseph Nahas | 3 | 68 | 21.60 |
| Michael Niemier | 4 | 191 | 31.85 |