Title
Design for testability for path delay faults in sequential circuits
Abstract
Abstruct-We experimentally study the reasons for low coverage of path delay faults in several sequential benchmark circuits. Causes for undetected faults are classified htto three categories: (A) Combinationally nonactivated paths, (B) Sequentially nonactivated paths, and (C) Unobservable fault effect. The type A faults can only be made detectable by modtfyhtg or resynthesizing the combinational logic as has been discussed by others. We fhtd that almost 80% of sequentially untested faults are in category B. Most are not activated because the two successive states necessary to create a transition and to propagate it through the path cannot be produced in the sequential circuit. We study the partial scan technique in which flipflops are scanned to break cycles and show that a substantial increase in the coverage of path delay faults is p~ible.
Year
DOI
Venue
1993
10.1145/157485.164973
DAC
Keywords
Field
DocType
sequential circuit,path delay fault,benchmark testing,sequential analysis,sequential circuits,propagation delay,design for testability,logic
Design for testing,Sequential logic,Propagation delay,Computer science,Algorithm,Combinational logic,Real-time computing,Electronic engineering,Electronic circuit,Unobservable,Benchmark (computing),Asynchronous circuit
Conference
ISBN
Citations 
PageRank 
0-89791-577-1
15
1.17
References 
Authors
9
3
Name
Order
Citations
PageRank
Tapan J. Chakraborty125826.11
Vishwani D. Agrawal23502470.06
Michael L. Bushnell346282.27