Tapan J. Chakraborty - Citegraph

Author Info

Name	Affiliation	Papers
TAPAN J. CHAKRABORTY	Lucent Technol, Whippany, NJ 07981 USA	17
Collaborators	Citations	PageRank
20	258	26.11
Referers	Referees	References
418	195	134

Search Limit

100418

Publications (17 rows)

Collaborators (20 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Functional Fmax test-time reduction using novel DFTs for circuit initialization	0	0.34	2013
A New Language Approach For Ijtag	0	0.34	2008
FPGA Prototyping of a Scan Based System-On-Chip Design	3	0.43	2007
A TMR Scheme for SEU Mitigation in Scan Flip-Flops	11	0.95	2007
Efficient Test Architecture based on Boundary Scan for Comprehensive System Test	0	0.34	2005
A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architecture	8	0.65	2002
Path delay fault simulation of sequential circuits	27	1.59	2000
Improving path delay testability of sequential circuits	5	0.48	2000
A BIST scheme for the detection of path-delay faults	6	0.59	1998
Effective Path Selection for Delay Fault Testing of Sequential Circuits	11	1.94	1997
Delay independent initialization of sequential circuits	2	0.51	1994
Partial scan testing with single clock control.	0	0.34	1993
Design for testability for path delay faults in sequential circuits	15	1.17	1993
On behavior fault modeling for digital designs	46	4.10	1991
Enhanced controllability for IDDQ test sets using partial scan	1	0.36	1991
Gentest: an automatic test-generation system for sequential circuits	115	11.15	1989
On behavior fault modeling for combinational digital designs	8	0.83	1988

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