Name
Title | ||
|---|---|---|
A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator |
Abstract | ||
|---|---|---|
A method is presented to accelerate test generation, which synthesizes a test-generation circuit S(C, F) that combines the original combinational circuit C (modified by programmable faults F) and peripheral circuits that automatically generate a test of C. The test patterns are generated by searching the inputs to expose faults to the outputs using an ultrahigh-speed simulator (SP) |
Year | DOI | Venue |
|---|---|---|
1988 | 10.1109/TEST.1988.207786 | ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing |
Keywords | Field | DocType |
test pattems,ultrahigh-speed logic simulator,ultrahigh-speed simulator,programmable faults f,peripheral circuit,original combinational circuit,test-generation circuit,combinational logic circuit,combinational circuit,combinational circuits,parallel processing,computational modeling,registers | Automatic test pattern generation,Digital electronics,Sequential logic,Logic optimization,Computer science,Programmable logic array,Electronic engineering,Combinational logic,Asynchronous circuit,Programmable logic device | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-8186-0870-6 | 12 |
PageRank | References | Authors |
1.13 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fumiyasu Hirose | 1 | 258 | 97.57 |
| Koichiro Takayama | 2 | 59 | 5.56 |
| Nobuaki Kawato | 3 | 105 | 79.03 |