Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006 | 173 | 18.30 | 2006 |
Speeding Up Look-up-Table Driven Logic Simulation | 0 | 0.34 | 1999 |
An approach to verify a large scale system-on-a-chip using symbolic model checking | 8 | 2.36 | 1998 |
Acceleration Of Mincut Partitioning Using Hardware Cad Accelerator Tp5000 | 0 | 0.34 | 1997 |
Acceleration of behavioral simulation on simulation specific machines | 0 | 0.34 | 1997 |
CTL model checking based on forward state traversal | 36 | 3.77 | 1996 |
Logic synthesis for a single large look-up table | 7 | 0.62 | 1995 |
Panel: New Research Problems in the Emerging Test Technology | 0 | 0.34 | 1995 |
Test pattern generation system for delay faults using a high speed simulation processor 'SP' | 0 | 0.34 | 1992 |
A high-speed test-generation method using a test generation circuit. | 0 | 0.34 | 1990 |
Simulation processor "SP". | 7 | 0.81 | 1989 |
A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator | 12 | 1.13 | 1988 |
Efficient placement and routing techniques for master slice LSI | 15 | 68.55 | 1980 |