Name
Abstract | ||
|---|---|---|
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem because of the inherent computational cost, and because in practice false paths are not specified one full path at a time. Instead designers use generalized false paths, which represent a set of paths. For instance the SDC format (Synopsys Design Constraint) specifies false path exceptions using a “-from -through -to” syntax that applies on sets of pins, often using wildcards to denote these sets. This represents many (usually hundreds to thousands) actual full paths. This paper proposes a method to verify generalized false paths in a very efficient manner. It is shown to be about 10x faster than the current state-of-the-art, making false path verification an overnight task or less for multi-million gate designs. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1837274.1837321 | Design Automation Conference |
Keywords | Field | DocType |
actual full path,false path verification,chip failure,false path,sdc format,full path,timing exception verification,efficient algorithm,synopsys design constraint,false path exception,practice false path,propagation delay,chip,logic design,correctness,logic gates,set theory,semantics,sat,algorithm design and analysis,formal verification | Set theory,Logic gate,Wildcard character,Computer science,Correctness,Algorithm,Chip,Theoretical computer science,Syntax,Semantics,Formal verification | Conference |
ISSN | ISBN | Citations |
0738-100X | 978-1-4244-6677-1 | 7 |
PageRank | References | Authors |
0.54 | 8 | 1 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Olivier Coudert | 1 | 665 | 104.87 |