Name
Abstract | ||
|---|---|---|
This paper introduces the concept of hierarchical testabilityof data paths for delay faults. A definition of hierarchicallytwo-pattern testable (HTPT) data path is developed. Also, adesign for testability (DFT) method is presented to augmenta data path to an HTPT one. The DFT method incorporatesa graph-based analysis of an HTPT data path and makes useof some graph algorithms. The proposed method can providethe similar advantages of the enhanced scan approach at thecost of much lower hardware overhead. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/ATS.2001.990251 | Asian Test Symposium |
Keywords | DocType | Volume |
data path,hierarchically two-pattern testable,delay fault,hierarchical two-pattern testability,dft method incorporatesa,hierarchical testabilityof data path,graph algorithm,lower hardware overhead,hierarchical testability,graph-based analysis,data paths,htpt data path,dft method,hierarchicallytwo-pattern testable,design for testability,registers,graph theory,automatic test pattern generation,algorithm design and analysis,high level synthesis,robustness,hardware,atpg,register transfer level | Conference | E85D |
Issue | ISSN | ISBN |
6 | 1745-1361 | 0-7695-1233-x |
Citations | PageRank | References |
10 | 0.64 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Md. Altaf-Ul-Amin | 1 | 218 | 14.31 |
| Satoshi Ohtake | 2 | 135 | 21.62 |
| Hideo Fujiwara | 3 | 184 | 20.31 |