Abstract | ||
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Boolean matching is a fundamental problem in FPGA synthesis, but existing Boolean matchers are not scalable to complex PLBs (programmable logic blocks) and large circuits. This paper proposes a filter-based Boolean matching method, F-BM, which accelerates Boolean matching using lookup tables implemented by Bloom filters storing pre-calculated matching results. To show the effectiveness of the proposed F-BM, a post-mapping re-synthesis minimizing area which employs Boolean matching as the kernel has been implemented. Tested on a broad selection of benchmarks, the re-synthesizer using F-BM is 80X faster with 0.5% more area, compared with the one using a SAT-based Boolean matcher. |
Year | DOI | Venue |
---|---|---|
2010 | 10.1587/transfun.E93.A.1775 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
FPGA, Boolean matching, Bloom filter, SAT, re-synthesis | Bloom filter,Lookup table,Discrete mathematics,Boolean circuit,Algorithm,Theoretical computer science,Combinational logic,Standard Boolean model,Circuit minimization for Boolean functions,And-inverter graph,Mathematics,Programmable logic device | Journal |
Volume | Issue | ISSN |
E93A | 10 | 0916-8508 |
Citations | PageRank | References |
1 | 0.35 | 12 |
Authors | ||
5 |
Name | Order | Citations | PageRank |
---|---|---|---|
Chun Zhang | 1 | 213 | 51.33 |
Yu Hu | 2 | 75 | 9.62 |
Lingli Wang | 3 | 86 | 25.42 |
Lei He | 4 | 1015 | 86.74 |
Jiarong Tong | 5 | 68 | 11.74 |