Name
Abstract | ||
|---|---|---|
In this paper, we first present an efficient algorithm for the gate sizing problem. Then we propose an algorithm which performs delay and area optimization for a given compact placement by resizing and relocating cells in the circuit layout. Since the gate sizing procedure is embedded within the placement adjustment process, interconnect capacitance information is included in the gate size selection process. As a result, the algorithm is able to obtain superior solutions. |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/ICCAD.1994.629757 | ICCAD |
Keywords | Field | DocType |
area optimization,circuit layout,gate resizing,capacitance information,gate size selection process,compact placement,superior solution,efficient algorithm,placement adjustment process,capacitance,circuits,linear programming,logic gates,cost function | Delay calculation,Relocation,Logic gate,Capacitance,Resizing,Computer science,Electronic engineering,Linear programming,Interconnection,Electronic circuit | Conference |
ISSN | ISBN | Citations |
1063-6757 | 0-8186-3010-8 | 5 |
PageRank | References | Authors |
0.84 | 8 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Weitong Chuang | 1 | 72 | 8.69 |
| Ibrahim N. Hajj | 2 | 572 | 79.52 |