| Beyond SPICE. | 0 | 0.34 | 2017 |
| Extended Nodal Analysis | 0 | 0.34 | 2012 |
| Post-route gate sizing for crosstalk noise reduction | 14 | 0.88 | 2003 |
| A technique for improving dual-output domino logic | 1 | 0.37 | 2002 |
| Early probabilistic noise estimation for capacitively coupled interconnects | 8 | 0.64 | 2002 |
| Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model | 17 | 0.89 | 2002 |
| Estimation of state line statistics in sequential circuits | 4 | 0.48 | 2002 |
| Simultaneous switching noise and resonance analysis of on-chip power distribution network | 6 | 0.57 | 2002 |
| A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model | 0 | 0.34 | 2001 |
| A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance | 2 | 0.39 | 2001 |
| Maximum Power Supply Noise Estimation In Vlsi Circuits Using Multimodal Genetic Algorithms | 2 | 0.55 | 2001 |
| Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits | 4 | 1.04 | 2001 |
| Current-Mode Threshold Logic Gates | 8 | 0.77 | 2000 |
| Using dynamic cache management techniques to reduce energy in general purpose processors | 19 | 1.27 | 2000 |
| An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling | 17 | 1.52 | 2000 |
| Multiple design error diagnosis and correction in digital VLSI circuits | 11 | 0.80 | 1999 |
| Low-Power Distributed Arithmetic Architectures Using Non-Uniform Memory Partitioning | 2 | 0.42 | 1999 |
| An optimization technique for dual-output domino logic | 1 | 0.39 | 1999 |
| A coding framework for low-power address and data busses | 114 | 7.09 | 1999 |
| An exact analytical time-domain model of distributed RC interconnects for high speed nonlinear circuit applications | 0 | 0.34 | 1999 |
| An Analytical, Transistor-Level Energy Model For Sram-Based Caches | 4 | 0.63 | 1999 |
| Correcting multiple design errors in digital VLSI circuits | 5 | 0.61 | 1999 |
| Design error diagnosis and correction via test vector simulation | 63 | 3.01 | 1999 |
| A reduced-order scheme for coupled lumped-distributed interconnect simulation | 0 | 0.34 | 1999 |
| Information-theoretic bounds on average signal transition activity [VLSI systems] | 19 | 2.06 | 1999 |
| Decorrelating (DECOR) transformations for low-power adaptive filters | 3 | 0.84 | 1998 |
| Diagnosis and correction of multiple logic design errors in digital circuits | 21 | 1.47 | 1997 |
| Analytical estimation of transition activity from word-level signal statistics | 15 | 1.34 | 1997 |
| GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/I/sub DDQ/ testing environment | 4 | 0.49 | 1997 |
| A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits | 19 | 1.50 | 1997 |
| Achievable bounds on signal transition activity | 10 | 2.21 | 1997 |
| Power estimation in sequential circuits | 42 | 6.69 | 1995 |
| Delay And Area Optimization For Compact Placement By Gate Resizing And Relocation | 5 | 0.84 | 1994 |
| Logic design error diagnosis and correction | 27 | 2.10 | 1994 |
| Diagnosis and Correction of Logic Design Errors in Digital Circuits | 40 | 3.29 | 1993 |
| Improved techniques for probabilistic simulation including signal correlation effects | 10 | 5.28 | 1993 |
| A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area | 9 | 1.20 | 1993 |
| Parallel-concurrent fault simulation | 4 | 1.39 | 1993 |
| ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits | 10 | 1.23 | 1992 |
| A multilevel parallel solver for block tridiagonal and banded linear systems | 7 | 0.87 | 1990 |
| A custom cell generation system for double-metal CMOS technology | 1 | 0.36 | 1989 |
| Automatic mixed-mode timing simulation | 1 | 0.45 | 1989 |
| CREST-a current estimator for CMOS circuits | 23 | 21.90 | 1988 |
