Name
Abstract | ||
|---|---|---|
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estimator closely reflects both dynamic and static power contributed by various FPGA components in 0.1um technology. The power estimation error is 16.2% on average. Second, we present a low power high level synthesis system, named LOPASS, for FPGA designs. It includes two algorithms for power consumption reduction: (i) a simulated annealing engine that carries out resource selection, function unit binding, scheduling, register binding, and data path generation simultaneously to effectively reduce power; (ii) an enhanced weighted bipartite matching algorithm that is able to reduce the total amount of MUX ports by 22.7%. Experimental results show that LOPASS is able to reduce power consumption by 35.8% compared to the results of Synopsys' Behavioral Compiler. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1145/871506.871541 | ISLPED |
Keywords | Field | DocType |
low power,static power,power consumption reduction,various fpga component,fpga design,rt-level power estimator,fpga architecture,fpga circuit,power estimator,power consumption,power estimation error,low-power high-level synthesis,high level synthesis,low power electronics,network routing,bipartite matching,integrated circuit design,simulated annealing,field programmable gate arrays | Simulated annealing,Scheduling (computing),Computer science,High-level synthesis,Field-programmable gate array,Multiplexer,Real-time computing,Electronic engineering,Integrated circuit design,Low-power electronics,Estimator,Embedded system | Conference |
ISBN | Citations | PageRank |
1-58113-682-X | 61 | 3.07 |
References | Authors | |
18 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Deming Chen | 1 | 1432 | 127.66 |
| Jason Cong | 2 | 7069 | 515.06 |
| Yiping Fan | 3 | 456 | 25.67 |