Paper Info
Title
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
Abstract
The increasing complexity and the short life cycles of embedded systems are pushing the current system-on-chip designs towards a rapid increasing on the number of programmable processing units, while decreasing the gate count for custom logic. Considering this trend, this work proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the test access mechanism. Experimental results are based on ITC'02 benchmarks and on two open core processors compliant with MIPS and SPARC instruction set. The results show that the cooperative use of both the on-chip network and the embedded processors can increase the test parallelism and reduce the test time without additional cost in area and pins.
Year
DOI
Venue
2005
10.1109/DATE.2005.304
Clinical Orthopaedics and Related Research
Keywords
Field
DocType
multiple processors,test planning method,increasing complexity,test time,open core processors compliant,test source,on-chip network,test parallelism,embedded processor,test time reduction reusing,embedded system,test access mechanism,network on chip,software testing,life cycle,fpga,chip,programmable logic devices,intelligent networks,routing,embedded systems,hardware architecture,network on a chip,system testing,system on chip
Gate count,Test plan,Instruction set,Computer science,Real-time computing,Built-in self-test,Programmable logic device,Computer architecture,System on a chip,Parallel computing,Network on a chip,Field-programmable gate array,Embedded system
Conference
ISSN
ISBN
Citations 
Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)
0-7695-2288-2
2
PageRank 
References 
Authors
0.43
5
4
Name
Order
Citations
PageRank
Alexandre M. Amory111315.56
Marcelo Lubaszewski248347.66
Fernando Moraes372043.62
Edson I. Moreno4384.77