Name
Abstract | ||
|---|---|---|
A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1/(N×TDmax) to 1/(3TDmin), where TDmin and TDmax are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line. Fabricated in a 0.35 μm single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 μm×515 μm and consumes a maximum power of 132 mW at 130 MHz. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/JSSC.2002.800922 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
cmos analogue integrated circuits,cmos process,wide-range operation,0.35 micron,fixed latency,jitter,132 mw,harmonic locking,delay-locked loop,timing jitter,6 to 130 mhz,start-controlled circuit,delay lock loops,phase selection circuit,delay locked loop,circuits,delay lock loop,time measurement,phase locked loops,very large scale integration | Journal | 37 |
Issue | ISSN | Citations |
8 | 0018-9200 | 54 |
PageRank | References | Authors |
6.61 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hsiang-Hui Chang | 1 | 174 | 22.64 |
| Jyh-Woei Lin | 2 | 59 | 8.38 |
| Ching-Yuan Yang | 3 | 227 | 36.15 |
| Shen-Iuan Liu | 4 | 1378 | 200.41 |