Name
Abstract | ||
|---|---|---|
In this paper, we propose a multiple-fault-diagnosis methodology based on the analysis of failing patterns and the structure of diagnosed circuits. We do not consider the multiple-fault behavior explicitly, but rather partition the failing outputs and use an incremental simulation-based technique to diagnose failures one at a time. Our methodology can be further improved by selecting appropriate diagnostic test patterns. The n-detection tests allow us to apply a simple single-fault-based diagnostic algorithm, and yet achieve good diagnosability for multiple faults. Experimental results demonstrate that our technique is highly efficient and effective. It has an approximately linear time complexity with respect to the fault multiplicity and achieves a high diagnostic resolution for multiple faults. Real manufactured industrial chips affected by multiple faults can be diagnosed in minutes of central processing unit (CPU) time. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/TCAD.2005.854624 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
multiple-fault-diagnosis methodology,diagnostic test patterns,fault simulation,circuit diagnosis,fault multiplicity,multiple-fault diagnosis,failing pattern analysis,high diagnostic resolution,multiple fault,central processing unit,failure analysis,circuit complexity,linear time complexity,single-fault-based diagnostic algorithm,appropriate diagnostic test pattern,incremental simulation-based technique,circuit testing,logic testing,simple single-fault-based diagnostic algorithm | Journal | 25 |
Issue | ISSN | Citations |
3 | 0278-0070 | 23 |
PageRank | References | Authors |
0.97 | 29 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhiyuan Wang | 1 | 23 | 0.97 |
| Malgorzata Marek-Sadowska | 2 | 2272 | 213.72 |
| K. -H. Tsai | 3 | 23 | 0.97 |
| J. Rajski | 4 | 985 | 63.36 |