Name
Papers
Collaborators
J. RAJSKI
42
62
Citations 
PageRank 
Referers 
985
63.36
1432
Referees 
References 
723
589
Search Limit
1001000
Title
Citations
PageRank
Year
Cell-Aware Test392.062014
Low power programmable PRPG with enhanced fault coverage gradient20.382012
Low power test application with selective compaction in VLSI designs20.412012
Cell-aware Production test results from a 32-nm notebook processor20.412012
Reduced ATE Interface for High Test Data Compression20.392011
Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression240.882011
Fault Diagnosis For Embedded Read-Only Memories60.562009
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector260.862008
Low Power Scan Shift And Capture In The Edt Environment361.182008
Low-Power Test Data Application in EDT Environment Through Decompressor Freeze160.602008
Improving the Resolution of Single-Delay-Fault Diagnosis30.502008
Enhancing Delay Fault Coverage Through Low-Power Segmented Scan210.772007
Fault Diagnosis With Convolutional Compactors70.482007
Analysis and methodology for multiple-fault diagnosis230.972006
X-Press Compactor for 1000x Reduction of Test Data261.012006
Finite memory test response compactors for embedded test applications381.152005
Embedded deterministic test2547.202004
Ring generators - new devices for embedded test applications532.082004
Finding a common fault response for diagnosis during silicon debug10.352002
Cellular automata-based test pattern generators with phase shifters140.992000
Improving the proportion of at-speed tests in scan BIST80.552000
Testing of telecommunications hardware [Guest Editorial]00.341999
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs80.551999
Comparative study of CA-based PRPGs and LFSRs with phase shifters151.661999
STARBIST: scan autocorrelated random pattern generation221.601997
A self-driven test structure for pseudorandom testing of non-scan sequential circuits30.551996
A complexity analysis of sequential ATPG50.471996
Decompression of test data using variable-length seed LFSRs494.391995
Fault coverage analysis of RAM test algorithms71.241995
Software accelerated functional fault simulation for data-path architectures30.431995
Arithmetic built-in self test for high-level synthesis331.691995
On necessary and nonconflicting assignments in algorithmic test pattern generation232.031994
Delay-fault testability preservation of the concurrent decomposition and factorization transformations30.441994
Recursive pseudoexhaustive test pattern generation81.111993
Test responses compaction in accumulators with rotate carry adders251.631993
The testability-preserving concurrent decomposition and factorization of Boolean expressions404.381992
BIST of PCB interconnects using boundary-scan architecture170.941992
On the diagnostic properties of linear feedback shift registers161.871991
On the diagnostic resolution of signature analysis00.341990
A method to calculate necessary assignments in algorithmic test pattern generation509.971990
A method of fault analysis for test generation and fault diagnosis493.121988
The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's60.831986