Name
Title | ||
|---|---|---|
Communication Synthesis For Interconnect Minimization In Multicycle Communication Architecture |
Abstract | ||
|---|---|---|
In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle Communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative algorithm with regard of both spatial and temporal perspectives. It Features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1587/transfun.E92.A.3143 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
multicycle communication, communication synthesis, interconnect minimization, resource allocation, resource sharing, scheduling, routing | Architecture,Data transmission,Computer science,Scheduling (computing),Communication channel,Minification,Resource allocation,Router,Shared resource,Distributed computing | Journal |
Volume | Issue | ISSN |
E92A | 12 | 0916-8508 |
Citations | PageRank | References |
3 | 0.39 | 12 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ya-Shih Huang | 1 | 16 | 2.36 |
| Yu-Ju Hong | 2 | 99 | 8.29 |
| Juinn-Dar Huang | 3 | 270 | 27.42 |