Name
Abstract | ||
|---|---|---|
Model checking has received wide acceptance as a valuable technique in the eld of electronicdesign automation and is currently of growing interest in general systems design. Though itsconcepts and applications are well understood it often turns out that engineers have severeproblems with the specication process and the underlying notation, i.e., formulation andunderstanding of specications through means of temporal logic formulae. In this article, wepresent an approach for a natural... |
Year | Venue | Keywords |
|---|---|---|
2000 | MBMV | temporal logic,system design,model checking |
Field | DocType | Citations |
Formal equivalence checking,Abstraction model checking,Notation,Programming language,Model checking,Structured English,Computer science,Electronic design automation,Temporal logic,Symbolic trajectory evaluation | Conference | 12 |
PageRank | References | Authors |
1.08 | 7 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Stephan Flake | 1 | 241 | 22.77 |
| Wolfgang Müller | 2 | 89 | 12.68 |
| Jürgen Ruf | 3 | 122 | 23.04 |