Paper Info
Title
Supply noise suppression by triple-well structure
Abstract
This brief discusses the impact of twin- and triple-well structures on power supply noise, and a substrate model for simulating the power supply noise. We observed Vss noise reduction by the resistive network of the p-substrate and Vdd noise reduction by the junction capacitance of a triple-well structure on a 90-nm test chip. Measurement results also showed that the total noise reduction of a triple-well structure is superior to that of a twin-well structure. The measurement results correlate well with the results obtained from the power supply noise simulation using a hierarchical resistive mesh model. Our simulation-based verification indicates that in common CMOS design, a triple-well structure can reduce the power supply drop by 10%-40% or the decoupling capacitance area by 5%-10%. We also verified that supply drop sensitivity to variation of the well junction capacitance is sufficiently small and that supply noise reduction using a triple-well structure is robust to process variation.
Year
DOI
Venue
2013
10.1109/TVLSI.2012.2192458
VLSI) Systems, IEEE Transactions
Keywords
Field
DocType
triple-well structure,vdd noise reduction,power supply noise simulation,vss noise reduction,supply noise reduction,junction capacitance,total noise reduction,supply noise suppression,power supply noise,power supply drop,measurement result,noise,mesh generation,noise measurement,cmos integrated circuits,capacitance,noise reduction,integrated circuit design,substrate
Noise reduction,Flicker noise,Capacitance,Noise measurement,Computer science,Noise (electronics),Noise figure,Electronic engineering,Noise temperature,Diffusion capacitance
Journal
Volume
Issue
ISSN
21
4
1063-8210
Citations 
PageRank 
References 
6
0.70
10
Authors
4
Name
Order
Citations
PageRank
Yasuhiro Ogasahara1588.43
Masanori Hashimoto246279.39
Toshiki Kanamoto35011.68
Takao Onoye432968.21