| DC Magnetic Field-Based Analytical Localization Robust to Known Stationary Magnetic Object | 0 | 0.34 | 2022 |
| Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation | 0 | 0.34 | 2022 |
| Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling | 0 | 0.34 | 2022 |
| Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization | 0 | 0.34 | 2022 |
| Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections | 0 | 0.34 | 2022 |
| Minimizing Energy of DNN Training with Adaptive Bit-width and Voltage Scaling | 0 | 0.34 | 2021 |
| When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies | 0 | 0.34 | 2020 |
| Low-Cost Reservoir Computing using Cellular Automata and Random Forests | 0 | 0.34 | 2020 |
| Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction | 0 | 0.34 | 2020 |
| Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier | 0 | 0.34 | 2019 |
| Distilling Knowledge for Non-Neural Networks | 0 | 0.34 | 2019 |
| Mttf-Aware Design Methodology Of Adaptively Voltage Scaled Circuit With Timing Error Predictive Flip-Flop | 0 | 0.34 | 2019 |
| An Analytic Evaluation On Soft Error Immunity Enhancement Due To Temporal Triplication | 0 | 0.34 | 2018 |
| Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving. | 1 | 0.35 | 2018 |
| MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits. | 1 | 0.36 | 2018 |
| Hardware Architecture For High-Speed Object Detection Using Decision Tree Ensemble | 1 | 0.40 | 2018 |
| Comparing voltage adaptation performance between replica and in-situ timing monitors | 0 | 0.34 | 2018 |
| Sneak path free reconfiguration of via-switch crossbars based FPGA | 0 | 0.34 | 2018 |
| Interconnect Delay Analysis for RRAM Crossbar Based FPGA. | 0 | 0.34 | 2018 |
| Contributions of SRAM, FF and combinational circuit to chip-level neutron-induced soft error rate: - Bulk vs. FD-SOI at 0.5 and 1.0V - | 0 | 0.34 | 2017 |
| GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction. | 1 | 0.48 | 2017 |
| Critical path isolation for time-to-failure extension and lower voltage operation. | 1 | 0.36 | 2016 |
| Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits. | 0 | 0.34 | 2016 |
| A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch | 2 | 0.40 | 2016 |
| Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits | 0 | 0.34 | 2016 |
| Impact of package on neutron induced single event upset in 20 nm SRAM | 0 | 0.34 | 2015 |
| An oscillator-based true random number generator with process and temperature tolerance | 0 | 0.34 | 2015 |
| Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise | 1 | 0.37 | 2015 |
| Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis | 0 | 0.34 | 2015 |
| Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design And Its Irradiation Testing | 3 | 0.54 | 2014 |
| Comparative Evaluation Of Lifetime Enhancement With Fault Avoidance On Dynamically Reconfigurable Devices | 0 | 0.34 | 2014 |
| Edge-Over-Erosion Error Prediction Method Based On Multi-Level Machine Learning Algorithm | 0 | 0.34 | 2014 |
| Nbti Mitigation Method By Inputting Random Scan-In Vectors In Standby Time | 0 | 0.34 | 2014 |
| A Process And Temperature Tolerant Oscillator-Based True Random Number Generator | 4 | 0.47 | 2014 |
| Supply noise suppression by triple-well structure | 6 | 0.70 | 2013 |
| Pvt-Induced Timing Error Detection Through Replica Circuits And Time Redundancy In Reconfigurable Devices | 2 | 0.43 | 2013 |
| A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling | 6 | 0.64 | 2013 |
| Signal-Dependent Analog-To-Digital Conversion Based On Minimax Sampling | 2 | 0.40 | 2013 |
| Jitter amplifier for oscillator-based true random number generator | 3 | 0.53 | 2013 |
| Field Slack Assessment For Predictive Fault Avoidance On Coarse-Grained Reconfigurable Devices | 0 | 0.34 | 2013 |
| A 0.8-V 110-Na Cmos Current Reference Circuit Using Subthreshold Operation | 0 | 0.34 | 2013 |
| Jitter Amplifier for Oscillator-Based True Random Number Generator. | 0 | 0.34 | 2013 |
| Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability And C-Based Design | 0 | 0.34 | 2013 |
| Real-Time Supply Voltage Sensor for Detecting/Debugging Electrical Timing Failures | 1 | 0.36 | 2013 |
| Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture | 5 | 0.43 | 2013 |
| Power Gating Implementation For Supply Noise Mitigation With Body-Tied Triple-Well Structure | 0 | 0.34 | 2012 |
| Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits | 26 | 1.32 | 2012 |
| Stress Probability Computation For Estimating Nbti-Induced Delay Degradation | 1 | 0.37 | 2011 |
| Power gating implementation for noise mitigation with body-tied triple-well structure | 1 | 0.36 | 2011 |
| Device-parameter estimation with on-chip variation sensors considering random variability | 3 | 0.53 | 2011 |
