Name
Abstract | ||
|---|---|---|
An automated runtime power-gating scheme to reduce the leakage power in the active mode is presented in this paper. We propose a circuit that generates a sleep control signal from a clock-gating control signal automatically. By the combination of selective MT-CMOS scheme, the generated sleep control signal, and a novel flip-flop circuit with an additional latch function, a zero-wait transition from a sleep mode to an active mode is enabled. The additional latch function required for the zero-wait transition is achieved by only 6 transistors in addition to a conventional flip-flop. By the scheme, any design with the clock-gating scheme can be transformed automatically to a power-gated design while keeping the system operation the same in terms of the cycle accuracy. The scheme is applied to an MPEG4/H.264 audio/video codec and 21% power saving is achieved in the active mode while keeping the area overhead only 16% in a 90nm CMOS design. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ICCD.2007.4601928 | 2007 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, VOLS, 1 AND 2 |
Keywords | Field | DocType |
cmos integrated circuits,clock gating | Computer science,FLOPS,Active mode,Leakage power,CMOS,Electronic engineering,Real-time computing,Power gating,Transistor,Sleep mode,Codec | Conference |
ISSN | Citations | PageRank |
1063-6404 | 0 | 0.34 |
References | Authors | |
4 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mototsugu Hamada | 1 | 130 | 22.06 |
| Takeshi Kitahara | 2 | 82 | 25.52 |
| Naoyuki Kawabe | 3 | 86 | 8.79 |
| Hironori Sato | 4 | 9 | 2.15 |
| Tsuyoshi Nishikawa | 5 | 0 | 0.68 |
| Takayoshi Shimazawa | 6 | 37 | 11.55 |
| Takahiro Yamashita | 7 | 18 | 2.86 |
| Hiroyuki Hara | 8 | 67 | 7.06 |
| Yukihito Oowaki | 9 | 38 | 6.51 |