7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme | 6 | 0.46 | 2016 |
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture | 16 | 1.10 | 2015 |
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. | 12 | 0.75 | 2011 |
A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS | 16 | 1.23 | 2011 |
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. | 9 | 2.32 | 2010 |
An Automated Runtime Power-Gating Scheme | 0 | 0.34 | 2007 |
Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems | 8 | 0.86 | 2006 |