Name
Title | ||
|---|---|---|
Scalable object detection accelerators on FPGAs using custom design space exploration |
Abstract | ||
|---|---|---|
We discuss FPGA implementations of object (such as face) detectors in video streams using the accurate Haar-feature based algorithm. Rather than creating one implementation for one FPGA, we develop a method to generate a series of implementations that have different size and performance to target different FPGA devices. The automatic generation was enabled by custom design space exploration on a particular design problem relating to the communication architecture used to support different numbers of image classifiers. The exploration algorithm uses content information in each feature set to optimize and generate a scalable communication architecture. We generated fully-working implementations for Xilinx Virtex5 LX50T, LX110T, and LX155T FPGA devices, using various amounts of available device capacity, leading to speedups ranging from 0.6x to 25x compared to a 3.0 GHz Pentium 4 desktop machine. Automated generators that include custom design space exploration may become more necessary when creating hardware accelerators intended for use across a wide range of existing and future FPGA devices. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/SASP.2011.5941089 | SASP |
Keywords | Field | DocType |
video streams,custom design space exploration,xilinx virtex5 lx50t,haar-feature based algorithm,fpga device,exploration algorithm,scalable communication architecture,communication architecture,fpga implementation,automated generator,scalable object detection accelerator,different size,lx155t fpga device,object detection,future fpga device,haar transforms,field programmable gate arrays,pentium 4 desktop machine,different fpga device,particular design problem,different number,frequency 3 ghz,hardware accelerator,face,field programmable gate array,algorithm design,algorithm design and analysis,classification algorithms,computer architecture,pixel | Computer science,Real-time computing,Ranging,Computer hardware,Object detection,Computer architecture,Algorithm design,Parallel computing,Field-programmable gate array,FPGA prototype,Pentium,Design space exploration,Scalability | Conference |
ISBN | Citations | PageRank |
978-1-4577-1212-8 | 5 | 0.53 |
References | Authors | |
6 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chen Huang | 1 | 59 | 5.81 |
| Frank Vahid | 2 | 2688 | 218.00 |