Name
Abstract | ||
|---|---|---|
This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and analysis of the two-tone response envelope of the device under test (DUT). The response envelope is processed to obtain a simple digital signature sensitive to key specifications of the DUT. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ETSYM.2010.5512780 | Test Symposium |
Keywords | Field | DocType |
built-in self test,integrated circuit testing,radiofrequency integrated circuits,system-on-chip,RF block testing,SoC,built-in test core,device under test,low-cost signature test,two-tone response envelope analysis,RF BIST,RF test,Signature test | Response analysis,Transceiver,System on a chip,Device under test,Computer science,Radio frequency,Electronic engineering,Modulation,Digital signature,Built-in self-test | Conference |
ISSN | ISBN | Citations |
1530-1877 E-ISBN : 978-1-4244-5833-2 | 978-1-4244-5833-2 | 2 |
PageRank | References | Authors |
0.43 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Manuel J. Barragan Asian | 1 | 53 | 7.27 |
| Rafaella Fiorelli | 2 | 57 | 11.24 |
| Diego Vázquez | 3 | 136 | 15.33 |
| Adoración Rueda | 4 | 275 | 40.01 |
| José Luis Huertas | 5 | 77 | 9.97 |
| Barragan, M.J. | 6 | 2 | 0.43 |