Name
Abstract | ||
|---|---|---|
A 2-channel module for testing serial and parallel signals up to 12.8Gbps is described. It is intended to extend the capabilities of an existing 6.4Ghps ATE, serving as a plug-in module in an active device interface board (DIB). This prototype circuit provides (1) direct connections to ATE channels for DC parametrics and low-speed functional testing, (2) 2:1 multiplexing of 6.4Gbps to produce 12.8Gbps stimuli with picosecond deskew, jitter-injection, and amplitude adjustment, (3) 1:2 fanout of 12.8Gbps DUT response signals to allow testing by two 6.4Gbps ATE channels, (4) full-rate low-jitter active loopback path with amplitude adjustment, and (5) auxiliary outputs for parallel monitoring of both transmitted and received signals. The basic logical structure is presented, and features of the module construction are described. A novel high-bandwidth adjustable delay circuit is described, that is used for deskew and XOR-based multiplexing. The performance of the module is demonstrated between 5.0Gbps and 12.8Gbps. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TEST.2008.4700624 | 2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS |
Keywords | Field | DocType |
modules,functional testing,multiplexing,logic gates,jitter | Loopback,Logic gate,Prototype circuit,Computer science,Functional testing,Communication channel,Electronic engineering,Jitter,Multiplexing,Active devices | Conference |
ISSN | Citations | PageRank |
1089-3539 | 5 | 0.71 |
References | Authors | |
4 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| David C. Keezer | 1 | 68 | 17.00 |
| Dany Minier | 2 | 28 | 4.32 |
| Patrice Ducharme | 3 | 19 | 2.65 |
| A. M. Majid | 4 | 17 | 3.16 |