Paper Info
Title
Machine-Description Driven Compilers for EPIC and VLIW Processors
Abstract
In the past, due to the restricted gate count available on an inexpensive chip, embedded DSPs have had limited parallelism, few registers and irregular, incomplete interconnectivity. More recently, with increasing levels of integration, embedded VLIW processors have started to appear. Such processors typically have higher levels of instruction-level parallelism, more registers, and a relatively regular interconnect between the registers and the functional units. The central challenges faced by a code generator for an EPIC (Explicitly Parallel Instruction Computing) or VLIW processor are quite different from those for the earlier DSPs and, consequently, so is the structure of a code generator that is designed to be easily retargetable. In this paper, we explain the nature of the challenges faced by an EPIC or VLIW compiler and present a strategy for performing code generation in an incremental fashion that is best suited to generating high-quality code efficiently. We also describe the Operation Binding Lattice, a formal model for incrementally binding the opcodes and register assignments in an EPIC code generator. As we show, this reflects the phase structure of the EPIC code generator. It also defines the structure of the machine-description database, which is queried by the code generator for the information that it needs about the target processor. Lastly, we discuss our implementation of these ideas and techniques in Elcor, our EPIC compiler research infrastructure.
Year
DOI
Venue
1999
10.1023/A:1008842521805
Design Autom. for Emb. Sys.
Keywords
Field
DocType
Retargetable compilers,table-driven compilers,machine description,processor description,instruction-level parallelism,EPIC processors,VLIW processors,EPIC compilers,VLIW compilers,code generation,scheduling,register allocation
Instruction-level parallelism,Opcode,Computer architecture,Explicitly parallel instruction computing,Register allocation,Very long instruction word,Computer science,Parallel computing,Code generation,Chip,Compiler
Journal
Volume
Issue
ISSN
4
2-3
1572-8080
Citations 
PageRank 
References 
19
3.50
32
Authors
3
Name
Order
Citations
PageRank
B. Ramakrishna Rau11290183.17
Vinod Kathail234035.85
Shail Aditya325928.87