| Xilinx Vitis Unified Software Platform. | 3 | 0.48 | 2020 |
| A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform. | 7 | 0.51 | 2016 |
| SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC. | 6 | 0.51 | 2016 |
| UltraScale+ MPSoC and FPGA families | 3 | 0.44 | 2015 |
| Programming high performance signal processing systems in high level languages | 0 | 0.34 | 2010 |
| Architecture Exploration for Low Power Design | 0 | 0.34 | 2008 |
| Tutorial T8A: Automated Application Engine Synthesis from C Algorithms | 0 | 0.34 | 2007 |
| PICO: automatically designing custom computers | 95 | 6.21 | 2002 |
| PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators | 69 | 4.03 | 2002 |
| High-Level Synthesis of Nonprogrammable Hardware Accelerators | 57 | 3.47 | 2000 |
| Automatic Architectural Synthesis of VLIW and EPIC Processors | 42 | 8.98 | 1999 |
| Register Allocation in Hyper-block for EPIC Processors | 2 | 0.41 | 1999 |
| Fine Grained Register Allocation for EPIC Processors With Predication | 1 | 0.35 | 1999 |
| Machine-Description Driven Compilers for EPIC and VLIW Processors | 19 | 3.50 | 1999 |
| Meld Scheduling: A Technique for Relaxing Scheduling Constraints | 5 | 0.56 | 1998 |
| Techniques for critical path reduction of scalar programs | 2 | 0.38 | 1997 |
| Parallelization of Control Recurrences for ILP Processors. | 2 | 0.46 | 1996 |
| Meld scheduling: relaxing scheduling constraints across region boundaries | 3 | 1.10 | 1996 |
| Critical path reduction for scalar programs | 0 | 0.34 | 1995 |
| Height reduction of control recurrences for ILP processors | 17 | 1.89 | 1994 |
| Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism | 7 | 1.22 | 1993 |
