Name
Abstract | ||
|---|---|---|
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the increasing on-chip communication demand among the computation elements necessitates the use of scalable, highwidth network-on-chip (NoC) fabrics. As transistor feature sizes are further miniaturized leading to rapidly increasing amounts of on-chip resources, more complicated and powerful NoC architectures become feasible that can support more sophisticated and demanding applications. Given the myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening NoC design space to identify the architecture(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris(1), a system-level roadmap for on-chip interconnection networks that guides designers towards the most suitable network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that will run over this network(s). Polaris explores the plethora of NoC designs based on projections of network traffic, architectures, and process characteristics. While the Polaris roadmapping toolchain is extensible so new traffic, network designs, an processes can be added, the current version of the roadmap already incorporates 7,872 NoC design points. Polaris is rapid and iterates over all these NoC architectures within a tractable run time of 125 hours on a typical desktop machine, while maintaining high relative and absolute accuracies when validated against detailed NoC synthesis results. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ICCD.2006.4380806 | PROCEEDINGS 2006 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN |
Keywords | Field | DocType |
network design,system on a chip,cost effectiveness,chip,network on chip,logic design,design process,system design | Logic synthesis,Network planning and design,Computer science,Parallel computing,Network on a chip,Real-time computing,Chip,Interconnection,Design process,Toolchain,Scalability,Embedded system | Conference |
ISSN | Citations | PageRank |
1063-6404 | 20 | 1.35 |
References | Authors | |
20 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vassos Soteriou | 1 | 421 | 27.62 |
| Noel Eisley | 2 | 270 | 18.35 |
| Hangsheng Wang | 3 | 861 | 59.21 |
| Bin Li | 4 | 40 | 3.29 |
| Li-Shiuan Peh | 5 | 5077 | 398.57 |