Name
Abstract | ||
|---|---|---|
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primarily guided by the needs of single applications. However, as multiple applications or virtual machines (VMs) are consolidated on such a platform, researchers have observed that not all VMs or applications require significant amount of cache space. In order to take advantage of this phenomenon, we explore the use of asymmetric last-level caches in a CMP platform. While asymmetric cache CMPs provide the benefit of reduced power and area, it is important to build in hardware/software support to appropriately schedule applications on to cores with suitable cache capacity. In this paper, we address this problem with our ACCESS architecture comprising of: (a) asymmetric caches across a group of cores, (b) hardware support that enables prediction of cache performance on the different sized caches and (c) OS scheduler support to make use of the prediction capability and appropriately schedule applications on to core with suitable cache capacity. Measurements on a working prototype using SPEC2006 benchmarks show that our ACCESS architecture can effectively schedule jobs in an asymmetric cache CMP and provide 23% performance improvement compared to a naive scheduler, and is 97% close to an oracle scheduler in making schedules. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/HPCA.2011.5749757 | HPCA |
Keywords | Field | DocType |
asymmetric cache,spec2006 benchmarks,processor scheduling,access,microprocessor chips,cache storage,asymmetric last-level cache,os scheduler support,virtual machines,cache space,suitable cache capacity,cache performance,last-level cache,asymmetric cache cmp,vm,asymmetric cache cmps,chip multiprocessors,hardware support,smart scheduling,access architecture,virtual machine,schedules,computer architecture,hardware,linux,scheduling,benchmark testing | Cache invalidation,Cache pollution,Computer science,Cache,Parallel computing,Real-time computing,Page cache,Cache algorithms,Cache coloring,Bus sniffing,Smart Cache,Operating system | Conference |
ISSN | ISBN | Citations |
1530-0897 | 978-1-4244-9432-3 | 17 |
PageRank | References | Authors |
0.67 | 23 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaowei Jiang | 1 | 43 | 2.25 |
| Asit K. Mishra | 2 | 1216 | 46.21 |
| Li Zhao | 3 | 604 | 34.84 |
| Ravishankar Iyer | 4 | 720 | 35.52 |
| Zhen Fang | 5 | 91 | 7.62 |
| Sadagopan Srinivasan | 6 | 120 | 7.87 |
| Srihari Makineni | 7 | 600 | 37.89 |
| Paul Brett | 8 | 487 | 23.97 |
| Chita R. Das | 9 | 1046 | 45.21 |