Name
Abstract | ||
|---|---|---|
Hybrid embedded testbench acceleration (HETA), a new approach to reduce communication overhead in hardware accelerators, speeds up simulation of chip prototypes by avoiding the communication between hardware and software. Experimental results on an industry design show that the proposed HETA approach is about 10 times faster than a commercial hardware accelerator and with only 0.57% hardware overhead. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/MDT.2011.33 | IEEE Design & Test of Computers |
Keywords | Field | DocType |
hybrid testbench acceleration,hardware overhead,communication overhead,chip prototype,new approach,proposed heta approach,hardware accelerator,industry design show,commercial hardware accelerator,hybrid embedded testbench acceleration,power transmission lines,logic design,benchmark testing,testing,detectors,acceleration,emulation,central processing unit,chip,industrial design,functional verification | Logic synthesis,Functional verification,Central processing unit,Computer science,Intelligent verification,Chip,Software,Emulation,Hardware acceleration,Embedded system | Journal |
Volume | Issue | ISSN |
28 | 2 | 0740-7475 |
Citations | PageRank | References |
1 | 0.36 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chin-Lung Chuang | 1 | 10 | 1.96 |
| Chien-Nan Jimmy Liu | 2 | 97 | 27.07 |