| A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation | 0 | 0.34 | 2021 |
| Wire Load Oriented Analog Routing with Matching Constraints | 0 | 0.34 | 2020 |
| On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. | 1 | 0.37 | 2020 |
| Achieving Analog Layout Integrity through Learning and Migration Invited Talk | 0 | 0.34 | 2020 |
| A Structure-Based Methodology for Analog Layout Generation | 0 | 0.34 | 2019 |
| Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines | 0 | 0.34 | 2019 |
| Performance-preserved analog routing methodology via wire load reduction. | 0 | 0.34 | 2018 |
| Cluster-based delta-QMC technique for fast yield analysis. | 1 | 0.36 | 2017 |
| An Incremental Aging Analysis Method Based on Delta Circuit Simulation Technique | 0 | 0.34 | 2017 |
| An Incremental Simulation Technique Based On Delta Model For Lifetime Yield Analysis | 0 | 0.34 | 2017 |
| Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only) | 0 | 0.34 | 2015 |
| Low-noise analog synthesis platform for bio-signal acquisition system | 0 | 0.34 | 2015 |
| Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach | 1 | 0.37 | 2015 |
| Layout-aware analog synthesis environment with yield consideration | 0 | 0.34 | 2015 |
| Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits | 3 | 0.52 | 2015 |
| A novel design space reduction method for efficient simulation-based optimization | 1 | 0.37 | 2014 |
| Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics | 5 | 0.50 | 2014 |
| Simultaneous optimization for low dropout regulator and its error amplifier with process variation | 1 | 0.71 | 2014 |
| A layout-aware automatic sizing approach for retargeting analog integrated circuits | 3 | 0.41 | 2013 |
| Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs | 0 | 0.34 | 2013 |
| Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects | 1 | 0.35 | 2013 |
| Improving design verifiability by early RTL coverability analysis | 0 | 0.34 | 2012 |
| Peak wake-up current estimation at gate-level with standard library information | 0 | 0.34 | 2012 |
| Reducing test point overhead with don't-cares | 0 | 0.34 | 2012 |
| A fast heuristic approach for parametric yield enhancement of analog designs | 1 | 0.37 | 2012 |
| Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits | 0 | 0.34 | 2011 |
| ILP-based inter-die routing for 3D ICs | 3 | 0.45 | 2011 |
| Hybrid Testbench Acceleration for Reducing Communication Overhead | 1 | 0.36 | 2011 |
| Fast and accurate analysis of supply noise effects in PLL with noise interactions | 3 | 0.53 | 2010 |
| Dynamic IR drop estimation at gate level with standard library information | 4 | 0.72 | 2010 |
| Dynamic Supply Current Waveform Estimation With Standard Library Information | 2 | 0.41 | 2010 |
| Measurement And Evaluation Of The Bioelectrical Impedance Of The Human Body By Deconvolution Of A Square Wave | 0 | 0.34 | 2010 |
| Automatic circuit adjustment technique for process sensitivity reduction and yield improvement | 0 | 0.34 | 2010 |
| Behavior-level yield enhancement approach for large-scaled analog circuits | 0 | 0.34 | 2010 |
| Measuring The Transmission Characteristic Of The Human Body In An Electrostatic-Coupling Intra Body Communication System Using A Square Test Stimulus | 1 | 0.35 | 2010 |
| A tree-topology multiplexer for multiphase clock system | 8 | 0.66 | 2009 |
| Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging | 2 | 0.39 | 2009 |
| A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level | 0 | 0.34 | 2009 |
| A Low Jitter Self-Calibration Pll For 10-Gbps Soc Transmission Links Application | 0 | 0.34 | 2009 |
| Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design | 4 | 0.43 | 2009 |
| Analysis And Design Of Wide-Band Digital Transmission In An Electrostatic-Coupling Intra-Body Communication System | 2 | 0.54 | 2009 |
| Design of an all-digital LVDS driver | 3 | 0.49 | 2009 |
| Quick supply current waveform estimation at gate level using existed cell library information | 4 | 0.74 | 2008 |
| Long-Range Prediction For Real.-Time Mpeg Video Traffic: An H-Infinity Filter Approach | 0 | 0.34 | 2008 |
| Effective decap insertion in area-array SoC floorplan design | 2 | 0.40 | 2008 |
| An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning | 0 | 0.34 | 2008 |
| An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model | 0 | 0.34 | 2007 |
| On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design | 4 | 0.46 | 2007 |
| Observability Analysis on HDL Descriptions for Effective Functional Validation | 4 | 0.48 | 2007 |
| Using power gating techniques in area-array SoC floorplan design | 1 | 0.37 | 2007 |
