Title
A case study in reliability-aware design: a resilient LDPC code decoder
Abstract
Chip reliability becomes a great threat to the design of future microelectronic systems with the continuation of the progressive downscaling of CMOS technologies. Hence increasing the robustness of chip implementations in terms of error tolerance becomes an important issue. In this paper we present a case study in reliability-aware design tolerating transient errors. A state-of-the-art WiMAX channel decoder for LDPC codes is investigated on all design levels to increase its reliability for a given system performance with minimum hardware overhead. We show that an efficient exploitation of the algorithmic fault-tolerance yields a fairly small area overhead with nearly no degradation in communications performance even under high error injection rates.
Year
DOI
Venue
2008
10.1145/1403375.1403484
Proceedings of the conference on Design, automation and test in Europe
Keywords
Field
DocType
robustness,degradation,cmos technology,fault tolerant,system performance,fault tolerance,ldpc code,wimax,microelectronics,chip,integrated circuit design,decoding,hardware,cmos integrated circuits,active power
Low-density parity-check code,Computer science,CMOS,Chip,Real-time computing,WiMAX,Robustness (computer science),Integrated circuit design,Fault tolerance,Decoding methods,Embedded system
Conference
ISSN
Citations 
PageRank 
1530-1591
33
1.24
References 
Authors
9
3
Name
Order
Citations
PageRank
Matthias May1804.19
Matthias Alles21027.17
Norbert Wehn31165137.17