| Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node | 0 | 0.34 | 2022 |
| Multidimensional Minimum Euclidean Distance Approach Using Radar Reflectivities for Oil Slick Thickness Estimation | 0 | 0.34 | 2022 |
| DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM Analyses | 1 | 0.35 | 2022 |
| Beyond 100 Gbit/s Pipeline Decoders for Spatially Coupled LDPC Codes | 0 | 0.34 | 2022 |
| A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference | 1 | 0.36 | 2022 |
| Spatially Coupled Serially Concatenated Codes: Performance Evaluation and VLSI Design Tradeoffs | 0 | 0.34 | 2022 |
| HALF: Holistic Auto Machine Learning for FPGAs | 0 | 0.34 | 2021 |
| Exploiting Resiliency for Kernel-wise CNN Approximation enabled by Adaptive Hardware Design | 0 | 0.34 | 2021 |
| The Dynamic Random Access Memory Challenge in Embedded Computing Systems. | 1 | 0.38 | 2021 |
| Towards Fully Pipelined Decoding of Spatially Coupled Serially Concatenated Codes | 1 | 0.36 | 2021 |
| An Energy Efficient 3D-Heterogeneous Main Memory Architecture for Mobile Devices. | 0 | 0.34 | 2020 |
| When Massive GPU Parallelism Ain't Enough - A Novel Hardware Architecture of 2D-LSTM Neural Network. | 0 | 0.34 | 2020 |
| Multi-Valued Physical Unclonable Functions based on Dynamic Random Access Memory. | 0 | 0.34 | 2020 |
| eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex | 0 | 0.34 | 2020 |
| A 506Gbit/s Polar Successive Cancellation List Decoder with CRC. | 0 | 0.34 | 2020 |
| Efficient Generation of Application Specific Memory Controllers. | 0 | 0.34 | 2020 |
| Access-Aware Per-Bank DRAM Refresh for Reduced DRAM Refresh Overhead | 1 | 0.34 | 2020 |
| Real-Time Energy Efficient Hand Pose Estimation: A Case Study. | 0 | 0.34 | 2020 |
| Low-Complexity Computational Units For The Local-Sova Decoding Algorithm | 0 | 0.34 | 2020 |
| A Reduced-Complexity Projection Algorithm for ADMM-Based LP Decoding | 0 | 0.34 | 2020 |
| Efficient Hardware Architectures for 1D- and MD-LSTM Networks | 0 | 0.34 | 2020 |
| DRAMSys4.0 - A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator. | 0 | 0.34 | 2020 |
| A Lean, Low Power, Low Latency Dram Memory Controller For Transprecision Computing | 0 | 0.34 | 2019 |
| Polar Code Decoder Framework | 0 | 0.34 | 2019 |
| Fast validation of DRAM protocols with timed petri nets | 0 | 0.34 | 2019 |
| Adaptive Transient Computing for Power-Neutral Embedded Devices | 0 | 0.34 | 2019 |
| Speculative Temporal Decoupling Using Fork () | 0 | 0.34 | 2019 |
| Rapid Identification of Shared Memory in Multithreaded Embedded Systems with Static Scheduling. | 0 | 0.34 | 2019 |
| The Transprecision Computing Paradigm: Concept, Design, And Applications | 1 | 0.35 | 2018 |
| 25 Years of Turbo Codes: From Mb/s to beyond 100 Gb/s | 3 | 0.44 | 2018 |
| Integrating DRAM power-down modes in gem5 and quantifying their impact. | 0 | 0.34 | 2018 |
| Low-Latency CRC Calculation in Turbo-Code Decoding. | 0 | 0.34 | 2018 |
| FINN-L: Library Extensions and Design Trade-Off Analysis for Variable Precision LSTM Networks on FPGAs | 6 | 0.55 | 2018 |
| Improving The Error Behavior Of Dram By Exploiting Its Z-Channel Property | 0 | 0.34 | 2018 |
| A Reconfigurable Accelerator for Morphological Operations | 1 | 0.43 | 2018 |
| Bit-level pipelining for highly parallel turbo-code decoders: A critical assessment | 0 | 0.34 | 2017 |
| A Platform to Analyze DDR3 DRAM's Power and Retention Time. | 7 | 0.72 | 2017 |
| Using run-time reverse-engineering to optimize DRAM refresh. | 1 | 0.36 | 2017 |
| An advanced embedded architecture for connected component analysis in industrial applications. | 0 | 0.34 | 2017 |
| System simulation with gem5 and SystemC: The keystone for full interoperability | 1 | 0.36 | 2017 |
| A Wearable Flexible Sensor Network Platform for the Analysis of Different Sport Movements | 0 | 0.34 | 2017 |
| TensorQuant: A Simulation Toolbox for Deep Neural Network Quantization | 2 | 0.39 | 2017 |
| Enhanced Decoding For High-Rate Lte Turbo-Codes With Short Block Lengths | 0 | 0.34 | 2017 |
| The memory challenge in computing systems: A survey | 0 | 0.34 | 2017 |
| Exploiting Decoupled OpenCL Work-Items with Data Dependencies on FPGAs: A Case Study | 1 | 0.38 | 2017 |
| A Bank-Wise DRAM Power Model for System Simulations. | 4 | 0.39 | 2017 |
| IMU-based determination of fatigue during long sprint. | 0 | 0.34 | 2016 |
| Reverse Engineering of DRAMs: Row Hammer with Crosshair. | 14 | 0.51 | 2016 |
| Exploring system performance using elastic traces: Fast, accurate and portable | 1 | 0.37 | 2016 |
| Precision-tuning and hybrid pricer for closed-form solution-based Heston calibration. | 0 | 0.34 | 2016 |
