Name
Abstract | ||
|---|---|---|
Increasingly IC design is driven by integrated consumer devices, which rely on standard algorithms such as H.264, 802.1 In, or JPEG2000. These standards allow room for innovative implementation that can result in differentiated products. The architect's dilemma is that a disproportionate amount of the design time and the cost is spent on the hardware implementation and verification and not on algorithmic innovation. Automatic Application Engine Synthesis (AES) enables the creation of complex application engines such as an H.264 encoder directly from untimed C algorithms. It enables the designer to explore multiple design alternatives with different performance, area and power profiles in a very short period of time. This tutorial will focus on the use of AES methodology to design application engines consisting of configurable processors, hardware accelerators and complex interconnect, from C algorithms. The emphasis will be on describing techniques for synthesizing good HW from C code, competitive with manual design, for complex, multi-block hardware accelerators with the associated bus/memory/stream interconnect, as well as the verification and system validation of the resulting RTL. These blocks are crucial components of application engines, and they provide orders-of-magnitude improvement in performance and power compared to running the equivalent functions in software. Each topic will be presented taking examples from real-life designs. We will also present users' experiences in building a complete design using this methodology. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/VLSID.2007.173 | VLSI Design |
Keywords | Field | DocType |
application engine,design time,c algorithm,tutorial t8a,c algorithms,complex application engine,automated application engine synthesis,real-life design,complete design,manual design,multiple design alternative,ic design,c code,differentiated products,hardware accelerator,logic design | Logic synthesis,Standard algorithms,Computer science,Electronic engineering,Real-time computing,Software,JPEG 2000,System validation,Computer architecture,Algorithm,Integrated circuit design,Encoder,Interconnection,Embedded system | Conference |
ISSN | ISBN | Citations |
1063-9667 | 0-7695-2762-0 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vinod Kathail | 1 | 340 | 35.85 |
| Shail Aditya | 2 | 259 | 28.87 |
| Craig Gleason | 3 | 2 | 6.50 |
| Nagesh Chatekar | 4 | 0 | 0.34 |