Name
Abstract | ||
|---|---|---|
The effect of non-rectilinear gate (NRG) due to sub-wavelength lithograph dramatically increases the leakage current by more than 15X. To mitigate this penalty, we have developed a systematic procedure to optimize key layout parameters in regular layout with minimum area and speed overhead. As demonstrated in 65nm technology, the optimization of regular layout achieves more than 70% reduction in leakage under NRG, with area penalty of ~10% and marginal impact on circuit speed and active power.
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Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ASPDAC.2008.4483997 | ASP-DAC |
Keywords | Field | DocType |
non-rectilinear gate,nanoscale design,key layout parameter,leakage reduction,speed overhead,area penalty,marginal impact,circuit speed,active power,systematic procedure,minimum area,regular layout,design rule optimization,design optimization,leakage current,lithography,algorithm,integrated circuit layout,predictive models,nanolithography,space technology,design rules,formal verification | Integrated circuit layout,Nanoscopic scale,Leakage (electronics),Computer science,Electronic engineering,AC power,Nanolithography,Electrical engineering,Formal verification | Conference |
ISBN | Citations | PageRank |
978-1-4244-1922-7 | 7 | 1.03 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Anupama R. Subramaniam | 1 | 14 | 2.55 |
| Ritu Singhal | 2 | 32 | 3.77 |
| Chi-Chao Wang | 3 | 36 | 6.13 |
| Yu Cao | 4 | 329 | 29.78 |