Name
Abstract | ||
|---|---|---|
During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. Zn this paper, me take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/43.851998 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS |
Keywords | DocType | Volume |
buffers, integrated circuit interconnections, layout, routing | Journal | 19 |
Issue | ISSN | Citations |
7 | 0278-0070 | 5 |
PageRank | References | Authors |
0.59 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hai Zhou | 1 | 437 | 42.37 |
| Martin D. F. Wong | 2 | 3525 | 363.70 |
| I-Min Liu | 3 | 273 | 18.94 |
| Adnan Aziz | 4 | 1778 | 149.76 |